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rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a cmos 80 mhz, triple 10-bit video dacs adv7121/adv7122 ? analog devices, inc., 1996 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 adv7121 functional block diagram pixel input port ior iog iob r0 r9 clock 10 adv7121 v ref g0 g9 10 b0 b9 10 fs adjust 10 10 10 v aa reference amplifier comp dac dac red register blue register green register dac gnd adv7122 functional block diagram pixel input port ior iog iob r0 r9 clock 10 sync adv7122 gnd g0 g9 10 b0 b9 10 blank fs adjust 10 10 10 v aa reference amplifier comp dac dac red register blue register control register green register dac sync control v ref features 80 mhz pipelined operation triple 10-bit d/a converters rs-343a/rs-170 compatible outputs ttl compatible inputs +5 v cmos monolithic construction 40-pin dip package (adv7121) 44-pin plcc package (adv7122) 48-lead tqfp (adv7122) applications high definition television (hdtv) high resolution color graphics cae/cad/cam applications image processing instrumentation video signal reconstruction direct digital synthesis (dds) i/q modulation speed grades 80 mhz 50 mhz 30 mhz adv is a registered trademark of analog devices, inc. *speed grades up to 140 mhz are also available on special request. please contact analog devices or its representatives for details. general description the adv7121/adv7122 (adv ? ) is a video speed, digital-to- analog converter on a single monolithic chip. the part is specifi- cally designed for high resolution color graphics and video systems including high definition television (hdtv). it is also ideal for any application requiring a low cost, high speed dac function especially in communications. it consists of three, high speed, 10-bit, video d/a converters (rgb), a standard ttl input interface and high impedance, analog output, current sources. the adv7121/adv7122 has three separate, 10-bit, pixel input ports, one each for red, green and blue video data. a single +5 v power supply, an external 1.23 v reference and pixel clock input is all that is required to make the part operational. the adv7122 has additi onal video control signals, composite sy nc and blank . the adv7121/adv7122 is capable of generating rgb video output signals which are compatible with rs-343a, rs-170 and most proposed production system hdtv video standards, in- cluding smpte 240m. the adv7121/adv7122 is fabricated in a +5 v cmos pro- cess. its monolithic cmos construction ensures greater func- tionality with low power dissipation. the adv7121 is packaged in a 0.6", 40-pin plastic dip package. the adv7122 is pack- aged in a 44-pin plastic leaded (j-lead) chip carrier, plcc, and 48-lead thin quad flatpack (tqfp). product highlights 1. fast video refresh rate, 80 mhz. 2. guaranteed monotonic to 10 bits. ten bits of resolution al- lows for implementation of linearization functions such as gamma correction and contrast enhancement. 3. compatible with a wide variety of high resolution color graphics systems including rs-343a/rs-170 and the pro- posed smpte 240m standard for hdtv.
rev. b C2C adv7121Cspecifications parameter k version units test conditions/comments static performance resolution (each dac) 10 bits accuracy (each dac) integral nonlinearity, inl 2 lsb max differential nonlinearity, dnl 1 lsb max guaranteed monotonic gray scale error 5 % gray scale max max gray scale current = (v ref * 7,969/r set ) ma coding binary digital inputs input high voltage, v inh 2 v min input low voltage, v inl 0.8 v max input current, i in 1 m a max v in = 0.4 v or 2.4 v input capacitance, c in 2 10 pf max analog outputs gray scale current range 15 ma min 22 ma max output current white level 16.74 ma min typically 17.62 ma 18.50 ma max black level 0 m a min typically 5 m a 50 m a max lsb size 17.28 m a typ dac to dac matching 5 % max typically 2% output compliance, v oc C1 v min +1.4 v max output impedance, r out 2 100 k w typ output capacitance, c out 2 30 pf max i out = 0 ma voltage reference voltage reference range, v ref 1.14/1.26 v min/v max v ref = 1.235 v for specified performance input current, i vref C5 ma typ power requirements v aa 5 v nom i aa 125 ma max typically 80 ma: 80 mhz parts 100 ma max typically 70 ma: 50 mhz & 35 mhz parts power supply rejection ratio 2 0.5 %/% max typically 0.12 %/%: f = 1 khz, comp = 0.1 m f power dissipation 625 mw max typically 400 mw: 80 mhz parts 500 mw max typically 350 mw: 50 mhz & 35 mhz parts dynamic performance glitch impulse 2, 3 50 pv secs typ dac noise 2, 3, 4 200 pv secs typ analog output skew 2 ns max typically 1 ns notes 1 temperature range (t min to t max ): 0 c to +70 c. 2 sample tested at +25 c to ensure compliance. 3 ttl input values are 0 to 3 volts, with input rise/fall times 3 ns, measured between the 10% and 90% points. timing reference points at 50% for inputs and outputs. see timing notes in figure 1. 4 this includes effects due to clock and data feedthrough as well as rgb analog crosstalk. specifications subject to change without notice. (v aa = +5 v 6 5%; v ref = +1.235 v; r l = 3.75 v , c l = 10 pf; r set = 560 v . all specifications t min to t max 1 unless otherwise noted.)
adv7121/adv7122 C3C rev. b parameter k version units test conditions/comments static performance resolution (each dac) 10 bits accuracy (each dac) integral nonlinearity, inl 2 lsb max differential nonlinearity, dnl 1 lsb max guaranteed monotonic gray scale error 5 % gray scale max max gray scale current: iog = (v ref *12.082/r set ) ma max gray scale current: ior, iob = (v ref *8,627/r set ) ma coding binary digital inputs input high voltage, v inh 2 v min input low voltage, v inl 0.8 v max input current, i in 1 m a max v in = 0.4 v or 2.4 v input capacitance, c in 2 10 pf max analog outputs gray scale current range 15 ma min 22 ma max output current white level relative to blank 17.69 ma min typically 19.05 ma 20.40 ma max white level relative to black 16.74 ma min typically 17.62 ma 18.50 ma max black level relative to blank 0 95 ma min typically 1.44 ma 1.90 ma max black level on ior, iob 0 m a min typically 5 m a 50 m a max black level on iog 6.29 ma min typically 7.62 ma 9.5 ma max sync level on iog 0 m a min typically 5 m a 50 m a max lsb size 17.28 m a typ dac to dac matching 5 % max typically 2% output compliance, v oc C1 v min +1.4 v max output impedance, r out 2 100 k w typ output capacitance, c out 2 30 pf max i out = 0 ma voltage reference voltage reference range, v ref 1.14/1.26 v min/v max v ref = 1.235 v for specified performance input current, i vref C5 ma typ power requirements v aa 5 v nom i aa 125 ma max typically 80 ma: 80 mhz parts 100 ma max typically 70 ma: 50 mhz & 35 mhz parts power supply rejection ratio 2 0.5 %/% max typically 0.12%/%: f = 1 khz, comp = 0.01 m f power dissipation 625 mw max typically 400 mw: 80 mhz parts 500 mw max typically 350 mw: 50 mhz & 35 mhz parts dynamic performance glitch impulse 2, 3 50 pv secs typ dac noise 2, 3, 4 200 pv secs typ analog output skew 2 ns max typically 1 ns notes 1 temperature range (t min to t max ) 0 c to +70 c. 2 sample tested at +25 c to ensure compliance. 3 ttl input values are 0 to 3 volts, with input rise/fall times 3 ns, measured between the 10% and 90% points. timing reference points at 50% for inputs and outputs. see timing notes in figure 1. 4 this includes effects due to clock and data feedthrough as well as rgb analog crosstalk. specifications subject to change without notice adv7122Cspecifications (v aa = +5 v 6 5%; v ref = +1.235 v; r l = 37.5 v , c l = 10 pf; r set = 560 v . all specifications t min to t max 1 unless otherwise noted.)
adv7121/adv7122 C4C rev. b timing characteristics 1 (v aa = +5 v 6 5%; v ref = +1.235 v; r l = 37.5 v , c l = 10 pf; r set = 560 v . all specifications t min to t max 2 unless otherwise noted.) parameter 80 mhz version 50 mhz version 30 mhz version units conditions/comments fmax 80 50 30 mhz max clock rate t 1 3 6 8 ns min data & control setup time t 2 2 2 2 ns min data & control hold time t 3 12.5 20 33.3 ns min clock cycle time t 4 4 7 9 ns min clock pulse width high time t 5 4 7 9 ns min clock pulse width low time t 6 30 30 30 ns max analog output delay 20 20 20 ns typ t 7 3 3 3 ns max analog output rise/fall time t 8 3 12 15 15 ns typ analog output transition time notes 1 ttl input values are 0 to 3 volts, with input rise/fall times 3 ns, measured between the 10% and 90% points. timing reference points at 50% for inputs and outputs. see timing notes in figure 1. 2 temperature range (t min to t max ): 0 c to +70 c. 3 sample tested at +25 c to ensure compliance. specifications subject to change without notice. clock data digital inputs (r0?9, g0?9, b0?9; sync, blank) t 4 t 5 t 6 t 2 t 1 t 8 t 7 analog outputs (ior, iog, iob) t 3 1. output delay (t 6 ) measured from the 50% point of the rising edge of the clock to the 50% point of full-scale transition. 2. transition time (t 8 ) measured from the 50% point of full-scale transition to within 2% of the final output value. 3. output rise/fall time (t 7 ) measured between the 10% and 90% points of full-scale transition. 4 sync and blank digital inputs are not provided on notes figure 1. video input/output timing recommended operating conditions parameter symbol min typ max units power supply v aa 4.75 5.00 5.25 volts ambient operating temperature t a 0 +70 c output load r l 37.5 w reference voltage v ref 1.14 1.235 1.26 volts
adv7121/adv7122 C5C rev. b absolute maximum ratings 1 v aa to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 v voltage on any digital pin . . . . . gnd C0.5 v to v aa + 0.5 v ambient operating temperature (t a ) . . . . . . . . 0 c to +70 c storage temperature (t s ) . . . . . . . . . . . . . . C65 c to +150 c junction temperature (t j ) . . . . . . . . . . . . . . . . . . . . +150 c soldering temperature (5 secs) . . . . . . . . . . . . . . . . . . . 220 c vapor phase soldering (1 minute) . . . . . . . . . . . . . . . . . 220 c ior, iob, iog to gnd 2 . . . . . . . . . . . . . . . . . . . 0 v to v aa notes 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 analog output short circuit to any power supply or common can be of an indefinite duration. pin configurations dip (n-40a) package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 40 39 38 37 36 35 34 33 32 31 30 29 15 16 17 18 19 20 top view (not to scale) adv7121 dip r5 r4 r3 r2 r1 r0 iob iog v aa gnd fs adjust ior clock b9 b8 b7 b6 b5 v ref comp r6 r7 r8 r9 g0 g1 g2 g3 g4 g6 g7 g8 g9 b0 b1 b2 b3 b4 g5 v aa plcc (p-44a) package 4321 28 27 26 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 adv7122 plcc top view (not to scale) 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 b2 b0 b3 r3 b1 g4 g5 g6 g7 blank sync clock r0 r1 r2 g8 g9 g1 g2 g3 comp fs adjust gnd gnd iog ior iob b9 r5 r4 g0 r8 r7 r6 r9 v aa v aa v aa v ref b6 b4 b7 b5 b8 warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the adv7121/adv7122 feature proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, p roper esd precaut ions are recommended to avoid performance degradation or loss of fu nctionality. ordering guide temperature package package model speed range * description option adv7121kn80 80 mhz 0 c to +70 c 40-pin plastic dip n-40a adv7121kn50 50 mhz 0 c to +70 c 40-pin plastic dip n-40a adv7121kn30 30 mhz 0 c to +70 c 40-pin plastic dip n-40a adv7122kp80 80 mhz 0 c to +70 c 44-lead plastic leaded chip carrier (plcc) p-44a adv7122kp50 50 mhz 0 c to +70 c 44-lead plastic leaded chip carrier (plcc) p-44a adv7122kp30 30 mhz 0 c to +70 c 44-lead plastic leaded chip carrier (plcc) p-44a adv7122kst50 50 mhz 0 c to +70 c 48-lead thin quad flatpack (tqfp) st-48 ADV7122KST30 30 mhz 0 c to +70 c 48-lead thin quad flatpack (tqfp) st-48 *industrial temperature range (C40 c to +85 c) parts are also available to special ranges. please contact your local analog devices representative.
adv7121/adv7122 C6C rev. b pin function description pin mnemonic function blank * composite blank control input (ttl compatible). a logic zero on this control input drives the analog outputs, ior, iob and iog, to the blanking level. the blank signal is latched on the rising edge of clock. while blank is a logical zero, the r0Cr9, g0Cg9 and r0Cr9 pixel inputs are ignored. sync * composite sync control input (ttl compatible). a logical zero on the sync input switches off a 40 ire current source. this is internally connected to the iog analog output. sync does not override any other control or data input, therefore, it should only be asserted during the blanking interval. sync is latched on the rising edge of clock. if sync information is not required on the green channel, the sync input should be tied to logical zero. clock clock input (ttl compatible). the rising edge of clock latches the r0Cr9, g0Cg9, b0Cb9, sync and blank pixel and control inputs. it is typically the pixel clock rate of the video system. clock should be driven by a dedicated ttl buffer. r0Cr9, red, green and blue pixel data inputs (ttl compatible). pixel data is latched on the rising edge of clock. g0Cg9, r0, g0 and b0 are the least significant data bits. unused pixel data inputs should be connected to either the b0Cb9 regular pcb power or ground plane. ior, iog, iob red, green, and blue current outputs. these high impedance current sources are capable of directly driving a doubly terminated 75 w coaxial cable. all three current outputs should have similar output loads whether or not they are all being used. fs adjust full-scale adjust control. a resistor (r set ) connected between this pin and gnd, controls the magnitude of the full-scale video signal. note that the ire relationships are maintained, regardless of the full-scale output current. the relationship between r set and the full-scale output current on iog (assuming i sync is connected to iog) is given by: r set ( w ) = 12,082 v ref (v)/iog (ma) the relationship between r set and the full-scale output current on ior, iog and iob is given by: iog* (ma) = 12,082 v ref (v)/r set ( w ) ( sync being asserted) ior, iob (ma) = 8,628 v ref (v)/r set ( w ) the equation for iog will be the same as that for ior and iob when sync is not being used, i.e., sync tied permanently low. for the adv7121, all three analog output currents are as described by: ior, iog, iob (ma) = 7,969 v ref (v)/r set ( w ) comp compensation pin. this is a compensation pin for the internal reference amplifier. a 0.1 m f ceramic capacitor must be connected between comp and v aa . v ref voltage reference input. an external 1.23 v voltage reference must be connected to this pin. the use of an external resistor divider network is not recommended. a 0.1 m f decoupling ceramic capacitor should be connected between v ref and v aa . v aa analog power supply (5 v 5%). all v aa pins on the adv7121/adv7122 must be connected. gnd ground. all gnd pins must be connected. * sync and blank functions are not provided on the adv7121.
adv7121/adv7122 C7C rev. b terminology blanking level the level separating the sync portion from the video portion of the waveform. usually referred to as the front porch or back porch. at 0 ire units, it is the level which will shut off the pic- ture tube, resulting in the blackest possible picture. color video (rgb) this usually refers to the technique of combining the three pri- mary colors of red, green and blue to produce color pictures within the usual spectrum. in rgb monitors, three dacs are required, one for each color. sync signal ( sync ) the position of the composite video signal which synchronizes the scanning process. gray scale the discrete levels of video signal between reference black and reference white levels. a 10-bit dac contains 1024 different levels, while an 8-bit dac contains 256. raster scan the most basic method of sweeping a crt one line at a time to generate and display images. reference black level the maximum negative polarity amplitude of the video signal. reference white level the maximum positive polarity amplitude of the video signal. sync level the peak level of the sync signal. video signal that portion of the composite video signal which varies in gray scale levels between reference white and reference black. also referred to as the picture signal, this is the portion which may be visually observed. circuit description & operation the adv7121/adv7122 contains three 10-bit d/a converters, with three input channels, each containing a 10-bit register. also integrated on board the part is a reference amplifier. crt control functions blank and sync are integrated on board the adv7122. digital inputs thirty bits of pixel data (color information) r0Cr9, g0Cg9 and b0Cb9 are latched into the device on the rising edge of each clock cycle. this data is presented to the three 10-bit dacs and is then converted to three analog (rgb) output waveforms. see figure 2. the adv7122 has two additional control signals, which are latched to the analog video outputs in a similar fashion. blank and sync are each latched on the rising edge of clock to maintain synchronization with the pixel data stream. the blank and sync functions allow for the encoding of these video synchronization signals onto the rgb video output. this is done by adding appropriately weighted current sources to the analog outputs, as determined by the logic levels on the blank and sync digital inputs. figure 3 shows the analog output, rgb video waveform of the adv7121/adv7122. the influence of sync and blank on the analog video waveform is illustrated. table i details the resultant effect on the analog outputs of blank and sync . all these digital inputs are specified to accept ttl logic levels. clock input the clock input of the adv7121/adv7122 is typically the pixel clock rate of the system. it is also known as the dot rate. the dot rate, and hence the required clock frequency, will be determined by the on-screen resolution, according to the follow- ing equation: dot rate = ( horiz res ) ( vert res ) ( refresh rate )/ ( retrace factor ) horiz res = number of pixels/line. vert res = number of lines/frame. refresh rate = horizontal scan rate. this is the rate at which the screen must be refreshed, typ- ically 60 hz for a noninterlaced system or 30 hz for an interlaced system. retrace factor = total blank time factor. this takes into account that the display is blanked for a certain fraction of the total duration of each frame (e.g., 0.8). clock data digital inputs (r0?9, g0?9, b0?9; sync, blank) analog outputs (ior, iog, iob) figure 2. video data input/output
adv7121/adv7122 C8C rev. b if we, therefore, have a graphics system with a 1024 1024 resolution, a noninterlaced 60 hz refresh rate and a retrace fac- tor of 0.8, then: dot rate = 1024 1024 60/0.8 = 78.6 mhz the required clock frequency is thus 78.6 mhz. all video data and control inputs are latched into the adv7121/ adv7122 on the rising edge of clock, as previously de- scribed in the digital inputs section. it is recommended that the clock input to the adv7121/adv7122 be driven by a ttl buffer (e.g., 74f244). 92.5 ire 7.5 ire 40 ire white level black level blank level sync level 19.05 0.714 26.67 1.000 1.44 0.054 9.05 0.340 0 0 7.62 0.286 0 0 ma v ma v red, blue green notes 1. outputs connected to a doubly terminated 75 w load. 2. v ref = 1.235v, r set = 560 w . 3. rs?43a levels and tolerances assumed on all levels. figure 3. rgb video output waveform table ia. video output truth table for the adv7122 iog ior, iob dac description (ma)* (ma) sync blank input data white level 26.67 19.05 1 1 3ffh video video + 9.05 video + 1.44 1 1 data video to blank video + 1.44 video + 1.44 0 1 data black level 9.05 1.44 1 1 00h black to blank 1.44 1.44 0 1 00h blank level 7.62 0 1 0 xxh sync level 0 0 0 0 xxh *typical with full-scale iog = 26.67 ma. v ref = 1.235 v, r set = 560 w , i sync connected to iog. table ib. video output truth table for the adv7121 ior, iog, iob dac description (ma)* input data white level 17.62 3ff video video data video to black video data black level 0 00h *typical with full scale = 17.62 ma. v ref = 1.235 v, r set = 560 w .
adv7121/adv7122 C9C rev. b video synchronization & control the adv7122 has a single composite sync ( sync ) input con- trol. many graphics processors and crt controllers have the ability of generating horizontal sync (hsync), vertical sync (vsync) and composite sync . in a graphics system which does not automatically generate a composite sync signal, the inclusion of some additional logic circuitry will enable the generation of a composite sync signal. the sync current is internally connected directly to the iog output, thus encoding video synchronization information onto the green video channel. if it is not required to encode sync in- formation onto the adv7122, the sync input should be tied to logic low. reference input an external 1.23 v voltage reference is required to drive the adv7121/adv7122. the ad589 from analog devices is an ideal choice of reference. it is a two-terminal, low cost, tempera- ture compensated bandgap voltage reference which provides a fixed 1.23 v output voltage for input currents between 50 m a and 5 ma. figure 4 shows a typical reference circuit connection diagram. the voltage reference gets its current drive from the adv7121/adv7122s v aa through an onboard 1 k w resistor to the v ref pin. a 0.1 m f ceramic capacitor is required between the comp pin and v aa . this is necessary so as to provide com- pensation for the internal reference amplifier. a resistance r set connected between fs adjust and gnd determines the amplitude of the output video level according to equations 1 and 2 for the adv7122 and equation 3 for the adv7121: iog * ( ma ) = 12,082 v ref (v)/ r set ( w ) (1) ior, iob (ma) = 8,628 v ref (v)/r set ( w ) (2) ior, iog, iob (ma) = 7,969 v ref (v)/r set ( w ) (3) *o nly applies to the adv7122 when sync is being used. if sync is not being encoded onto the green channel, then equation 1 will be similar to equation 2. to dacs v aa v ref gnd 1k w fs adjust r set 560 w 500 w 100 w analog power plane comp 0.01 m f 5v + i ref ? 5ma ad589 (1.235v voltage reference) adv7121/adv7122* *additional circuitry, including decoupling components, excluded for clariity figure 4. reference circuit using a variable value of r set , as shown in figure 4, allows for accurate adjustment of the analog output video levels. use of a fixed 560 w r set resistor yields the analog output levels as quoted in the specification page. these values typically correspond to the rs-343a video waveform values as shown in figure 3. d/a converters the adv7121/adv7122 contains three matched 10-bit d/a converters. the dacs are designed using an advanced, high speed, segmented architecture. the bit currents corresponding to each digital input are routed to either the analog output (bit = 1) or gnd (bit = 0) by a sophisticated decoding scheme. as all this circuitry is on one monolithic device, matching be- tween the three dacs is optimized. as well as matching, the use of identical current sources in a monolithic design guaran- tees monotonicity and low glitch. the onboard operational am- plifier stabilizes the full-scale output current against temperature and power supply variations. analog outputs the adv7121/adv7122 has three analog outputs, correspond- ing to the red, green and blue video signals. the red, green and blue analog outputs of the adv7121/ adv7122 are high impedance current sources. each one of these three rgb current outputs is capable of directly driving a 37.5 w load, such as a doubly terminated 75 w coaxial cable. figure 5a shows the required configuration for each of the three rgb outputs connected into a doubly terminated 75 w load. this arrangement will develop rs-343a video output voltage levels across a 75 w monitor. a suggested method of driving rs-170 video levels into a 75 w monitor is shown in figure 5b. the output current levels of the dacs remain unchanged, but the source termination resistance, z s , on each of the three dacs is increased from 75 w to 150 w . dacs ior, iog, iob z o = 75 w (cable) z s = 75 w (source termination) termination repeated three times for red, green and blue dacs z l = 75 w (monitor) figure 5a. analog output termination for rs-343a dacs ior, iog, iob z o = 75 w (cable) z s = 150 w (source termination) termination repeated three times for red, green and blue dacs z l = 75 w (monitor) figure 5b. analog output termination for rs-170
adv7121/adv7122 C10C rev. b more detailed information regarding load terminations for vari- ous output configurations, including rs-343a and rs-170, is available in an application note entitled video formats & required load terminations available from analog devices, publication no. e1228C15C1/89. figure 3 shows the video waveforms associated with the three rgb outputs driving the doubly terminated 75 w load of fig- ure 5a. as well as the gray scale levels, black level to white level, the diagram also shows the contributions of sync and blank for the adv7122. these control inputs add appropri- ately weighted currents to the analog outputs, producing the specific output level requirements for video applications. table ia. details how the sync and blank inputs modify the output levels. gray scale operation the adv7121/adv7122 can be used for stand-alone, gray scale (monochrome) or composite video applications (i.e., only one channel used for video information). any one of the three channels, red, green or blue can be used to input the digital video data. the two unused video data channels should be tied to logical zero. the unused analog outputs should be terminated with the same load as that for the used channel. in other words, if the red channel is used and ior is terminated with a doubly terminated 75 w load (37.5 w ), iob and iog should be terminated with 37.5 w resistors. see figure 6. gnd adv7121/adv7122 r0 r9 g0 g9 b0 b9 video input doubly terminated 75 w load ior iog iob 37.5 w 37.5 w figure 6. input and output connections for stand-alone gray scale or composite video video output buffers the adv7121/adv7122 is specified to drive transmission line loads, which is what most monitors are rated as. the analog output configurations to drive such loads are described in the analog interface section and illustrated in figure 5. however, in some applications it may be required to drive long transmis- sion line cable lengths. cable lengths greater than 10 meters can attenuate and distort high frequency analog output pulses. the inclusion of output buffers will compensate for some cable distortion. buffers with large full power bandwidths and gains between 2 and 4 will be required. these buffers will also need to be able to supply sufficient current over the complete output voltage swing. analog devices produces a range of suitable op amps for such applications. these include the ad84x series of monol ithic op a mps. in very high frequency applications (80 mhz), the a d9617 is recommended. more information on line driver buffering circuits is given in the relevant op amp data sheets. use of buffer amplifiers also allows implementation of other video standards besides rs-343a and rs-170. altering the gain components of the buffer circuit will result in any desired video level. dacs z o = 75 w (cable) z s = 75 w (source termination) ad848 +v s 0.1 m f 0.1 m f ior, iog, iob 75 w 2 7 6 4 3 z 1 z l = 75 w (monitor) z 1 z 2 gain (g) = 1+ ? s z 2 figure 7. ad848 as an output buffer pc board layout considerations the adv7121/adv7122 is optimally designed for lowest noise performance, both radiated and conducted noise. to comple- ment the excellent noise performance of the adv7121/adv7122 it is imperative that great care be given to the pc board layout. figure 8 shows a recommended connection diagram for the adv7121/adv7122. the layout should be optimized for lowest noise on the adv7121/adv7122 power and ground lines. this can be achieved by shielding the digital inputs and providing good de- coupling. the lead length between groups of v aa and gnd pins should by minimized so as to minimize inductive ringing. ground planes the adv7121/adv7122 and associated analog circuitry, should have a separate ground plane referred to as the analog ground plane. this ground plane should connect to the regular pcb ground plane at a single point through a ferrite bead, as il- lustrated in figure 8. this bead should be located as close as possible (within 3 inches) to the adv7121/adv7122. the analog ground plane should encompass all adv7121/ adv7122 ground pins, voltage reference circuitry, power sup- ply bypass circuitry, the analog output traces and any output amplifiers. the regular pcb ground plane area should encompass all the digital signal traces, excluding the ground pins, leading up to the adv7121/adv7122. power planes the pc board layout should have two distinct power planes, one for analog circuitry and one for digital circuitry. the analog power plane should encompass the adv7121/adv7122 (v aa ) and all associated analog circuitry. this power plane should be connected to the regular pcb power plane (v cc ) at a single point through a ferrite bead, as illustrated in figure 8. this bead should be loc ated within three inc hes of the adv7121/adv7122. the pcb power plane should provide power to all digital logic on the pc board, and the analog power plane should provide power to all adv7121/adv7122 power pins, voltage reference circuitry and any output amplifiers. the pcb power and ground planes should not overlay portions of the analog power plane. keeping the pcb power and ground planes from overlaying the analog power plane will contribute to a reduction in plane-to-plane noise coupling.
adv7121/adv7122 C11C rev. b supply decoupling noise on the analog power plane can be further reduced by the use of multiple decoupling capacitors (see figure 8). optimum performance is achieved by the use of 0.1 m f ceramic capacitors. each of the two groups of v aa should be individually decoupled to ground. this should be done by placing the ca- pacitors as close as possible to the device with the capacitor leads as short as possible, thus minimizing lead inductance. it is important to note that while the adv7121/adv7122 con- tains circuitry to reject power supply noise, this rejection de- creases with frequency. if a high frequency switching power supply is used, the designer should pay close attention to reduce ing power supply noise. a dc power supply filter (murata bnx002) will provide emi suppression between the switching power supply and the main pcb. alternatively, consideration could be given to using a three terminal voltage regulator. digital signal interconnect the digital signal lines to the adv7121/adv7122 should be isolated as much as possible from the analog outputs and other analog circuitry. digital signal lines should not overlay the ana- log power plane. due to the high clock rates used, long clock lines to the adv7121/adv7122 should be avoided so as to minimize noise pickup. any active pull-up termination resistors for the digital inputs should be connected to the regular pcb power plane (v cc ), and not the analog power plane. analog signal interconnect the adv7121/adv7122 should be located as close as possible to the output connectors thus minimizing noise pickup and re- flections due to impedance mismatch. the video output signals should overlay the ground plane, and not the analog power plane, thereby maximizing the high fre- quency power supply rejection. for optimum performance, the analog outputs should each have a source termination resistance to ground of 75 w (doubly terminated 75 w configuration). this termination resistance should be as close as possible to the adv7121/adv7122 so as to minimize reflections. additional information on pcb design is available in an appli- cation note entitled design and layout of a video graphics system for reduced emi. this application note is available from analog devices, publication no. e1309C15C10/89. figure 8. adv7121/adv7122 typical connection diagram and component list gnd fs adjust ior iog iob ground adv7121/adv7122 c3 0.1 m f c5 0.1 m f z1 (ad589) r1 75 w r2 75 w r3 75 w c1 33 m f c2 10 m f comp c6 0.1 m f analog power plane l2 (ferrite bead) r0 r9 g0 g9 b0 b9 clock sync* blank* rgb video output video data inputs video control inputs analog ground plane c4 0.1 m f l1 (ferrite bead) *sync and blank functions are not provided on the adv7121. v aa v ref +5v (v cc ) r set 560 w component c1 c2 c3, c4, c5, c6 l1, l2 r1, r2, r3 r set z1 description 33 m f tantalum capacitor 10 m f tantalum 0.1 m f ceramic capacitor ferrite bead 75 w 1% metal film resistor 1.235v voltage reference 560 w 1% metal film resistor vendor part number fair-rite 274300111 or murata bl01/02/03 dale cmf-55c analog devices ad589jh dale cmf-55c
adv7121/adv7122 C12C rev. b outline dimensions dimensions shown in inches and (mm). 44-terminal plastic leaded chip carrier (p-44a) 40-pin plastic dip (n-40a) c1391C24C4/90 printed in u.s.a.

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